APPLY

Verification Engineer

R&D | Haifa

In this role, you will design and implement simulation/verification environments for complex logic modules/designs running on FPGAs to verify the correctness of the design.
    Requirements:
  • B.Sc. in electrical/computer engineering.
  • At least 3 years of experience in Logic Design Verification.
  • Experience with UVM System Verilog-based simulation tools.
  Advantages:
  • Knowledge of HDL logic design – vhdl/verilog.
  • Experience with video channels\systems.
  • Experience with medical systems design.

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